MulMapper: Towards an Automated FPGA-Based CNN Processor Generator Based on a Dynamic Design Space Exploration

摘要

Many enterprises are adopting deep learning algorithms in their everyday tasks faster than ever. Convolutional Neural Networks (CNNs) in particular are being used widely due to the impressive performance in various application areas. FPGAs, on the other hand, are becoming a promising hardware platform for various deep learning algorithms including CNN. However, optimized and efficient FPGA design requires an expert with hardware design skills. This is particularly a challenge for deep learning practitioners who would like to accelerate their algorithm without worrying about the underlying hardware knowledge required to accomplish that in FPGAs. In this work we are proposing an automated framework, MulMapper, that can generate a functional and synthesized CNN processor hardware IP (using Vivado HLS) for Zynq-based FPGAs, given Caffe-based CNN definition file. We created a dynamic and novel design space utilizing Target Device Resource, Target Core Mode and Target Data Width as design space dimensions. MulMapper explores the design space in these three dimensions and proposes the optimum design points. We tested MulMapper framework on common CNN architectures, LeNet, CNP and CIFAR-10. It has been verified that early-stage MulMapper can lead to synthesis of resource-optimized CNN processor hardware IP that can be used for many regular CNN variants. Comparison with the state-of-the-art shows that architectures generated using MulMapper obtained up to 25-29× DSP48 and 13-20× on-chip memory reduction, with up to 0.35 GOP/sec performance.