Positioning of Thermal Via Regions for Reducing Hotspot Temperature in 3D ICs

摘要

3D stacking of integrated circuits seems to be a main trend for increasing the processor performance. However, It results in power density increase inducing additional thermal issues that have to be overcome. In this paper we analyze the thermal behaviour of eight-core processor based on Intel Haswell architecture implemented as a 2D chip and as a 3D architecture with two layers. We implement special via regions in 3D structure in various configurations and we compare results to that obtained for 2D structure. We show that the peak temperature can be significantly reduced and locations of via regions notably affects temperature distribution inside the chip.