A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths

摘要

With the growing clock frequencies and complexity for VLSIs, transition fault testing is required. However, the number of untestable transition faults is generally much more than that of untestable stuck-at faults due to the circuit structures and functions of VLSIs. From the view point of current structural testing, transition fault coverage might be insufficient and potential timing defects might be escaped. Therefore, design-for-testability to improve transition fault coverage is important. In this paper, we propose a controller augmentation method in addition to scan design, to improve transition fault coverage with reducing the number of untestable faults. Experimental results on high-level synthesis benchmark circuits show that the transition fault coverage was improved by 4.75 and the number of untestable faults was reduced by 76.93% on average.