In this paper, an efficient hardware architecture of Sample Important Resample Particle Filter (SIRF) is presented. This architecture carries out the sampling, weighting, and output calculations steps concurrently. The resampling step is implemented in a massively parallel form. For weight computation step, piecewise linear function is used instead of the classical exponential function. This decreases the complexity of the architecture without degrading the results. The presented architecture allows efficient memory utilization in addition to resource saving. Synthesis results confirmed the resource reduction and speed up advantages of our design. The hardware implementation targeted an Enhanced PF for object tracking application. FPGA is used as the implementation hardware platform.
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